1. Field of the Invention
The present invention relates to an electronic ballast for controlling the intensity of a gas discharge lamp, specifically, an electronic dimming ballast having a boost converter adapted to operate over an increased range of output power.
2. Description of the Related Art
In order for a gas discharge lamp, such as a fluorescent lamp, to illuminate, the lamp is typically driven by a ballast. Electronic ballasts receive alternating-current (AC) mains line voltage from an AC power source and convert the AC mains line voltage to an appropriate voltage waveform to drive the lamp.
FIG. 1 is a simplified block diagram of a prior art electronic ballast 10 for driving a fluorescent lamp 15. The electronic ballast 10 comprises a “front-end” circuit 20 and a “back-end” circuit 40. The front-end circuit 20 includes a radio-frequency interference (RFI) filter 22 for minimizing the noise provided on the AC mains and a full-wave rectifier 24 for receiving the AC mains line voltage (e.g., 120 VAC) and generating a rectified voltage. The front-end circuit 20 also includes a boost converter 26, which boosts the magnitude of the rectified voltage above the peak of the line voltage to produce a direct-current (DC) bus voltage 32. The boost converter 26 also improves the total harmonic distortion (THD) and the power factor of the input current to the ballast 10.
The front end circuit 20 provides the DC bus voltage 32 to the back end circuit 40. A bus capacitor 30 (i.e., an energy storage device) is provided between the front end circuit 20 and the back end circuit 40 for filtering the DC bus voltage 32 and has a capacitance of, for example, 15 μF. The ballast back-end circuit 40 includes a switching inverter 42 for converting the DC bus voltage 32 to a high-frequency AC voltage, and an output circuit 44 (e.g., a resonant tank circuit having a relatively high output impedance) for coupling the high-frequency AC voltage to the electrodes of the lamp 15.
The ballast 10 further comprises a control circuit 50, which controls the operation of the switching inverter 42 and thus the intensity of the lamp 15. The control circuit 50 receives a phase control input (e.g., a phase controlled signal provided by a dimmer circuit) through a resistor R52 and a diode D54. The resistor R52 (e.g., 200 kΩ) forms a resistor divider with a resistor R56 (e.g., 6.67 kΩ) to scale the magnitude of the phase control input down to a level appropriate for the control circuit 50 to process. The phase control input is also provided to the boost converter 26. A power supply 58 is coupled to the output of the rectifier 24 and generates a DC voltage VCC (e.g., approximately 15 VDC) for powering the control circuit 50 and other low-voltage circuitry of the ballast 10.
The phase control input is representative of a desired intensity of the fluorescent lamp 15. The phase control input is preferably equal to substantially zero volts for a first portion of a half-cycle of the AC power source and equal to substantially the AC mains voltage for the rest of the half-cycle. The control circuit 50 is operable to control the intensity of the lamp 15 in response to amount of time that the phase control input is substantially equal to the AC mains voltage each half-cycle. The control circuit 50 is operable to control the intensity across a dimming range of the lamp 15 from a low-end (LE) intensity (i.e., a minimum non-zero intensity, such as 1%) to a high-end (HE) intensity (e.g., a maximum intensity, such as 100%).
FIG. 2 is a simplified schematic diagram of the boost converter 26 of the ballast 10. The output of the rectifier 24 is supplied to an inductor L1 (e.g., 810 μH), which is coupled in series with a boost diode D1 whose cathode is coupled to the bus capacitor 30. A power switching field-effect transistor (FET) Q1 (e.g., part number IRFS840 manufactured by International Rectifier) is coupled to the junction of the inductor L1 and the anode of the diode D1 to circuit common through a current sense resistor R1 (e.g., 0.281Ω). A control integrated circuit (IC) U1 (e.g., part number TDA4862 manufactured by Infineon Technologies) controls the operation of the transistor Q1. Specifically, a drive pin GTDRV of the control IC U1 is coupled to the gate of the transistor Q1 through a delay circuit 60, which will be described in greater detail below. The transistor Q1 is switched at a high frequency (e.g., 30 kHz) to provide the desired DC voltage across the bus capacitor 30, to achieve power factor correction (PFC) so that the AC input current to the ballast 10 closely follows the AC mains line voltage, and to minimize total harmonic distortion (THD) by maintaining the input current wave shape as sinusoidal. To prevent audible noise from being generated, the boost converter 26 preferably does not operate at a frequency of less than 20 KHz.
A first resistor divider provides an input pin MULTIN of the control IC U1 with a signal representative of the rectified voltage. The first resistor divider comprises two resistors R2, R3 having resistances of, for example, 996 kΩ and 10 kΩ, respectively. In order to achieve the desired magnitude of the bus voltage 32, the control IC 34 monitors a feedback voltage at a feedback pin VSENSE. The feedback voltage is produced by a second voltage divider comprising two resistors R4, R5 (e.g., 1.86 MΩ and 10 kΩ, respectively), and is also provided to a pin VAOUT of the control IC U1 through a capacitor C1 (e.g., 100 nF).
The boost converter 26 preferably operates in critical conduction mode, rather than continuous or discontinuous conduction modes. In continuous conduction mode, the current through the inductor L1 is continuous and does not fall to zero amps. In contrast, discontinuous conduction mode allows for the current through the inductor L1 to fall to zero amps and remain at zero for a period of time each switching cycle of the boost converter. Critical conduction mode is at the intersection of continuous and discontinuous conduction modes. The current through the inductor L1 is allowed to fall to zero amps, but does not remain at zero amps for a significant amount of time. The use of critical conduction mode in the boost converter 26 most effectively minimizes THD of the ballast 10 and provides a good trade-off between conduction losses and switching losses of the boost converter.
FIG. 3A is a current waveform 70 of the current through the inductor L1 while the boost converter 26 is operating in critical conduction mode. When the transistor Q1 is conductive, a current flows through the inductor L1, the transistor Q1, and the resistor R1, and increases with respect to time. A pin ISENSE of the control IC U1 receives the voltage across the resistor R1, which is representative of the current through the resistor R1 and the inductor L1. In critical conduction mode, the charging current through the inductor L1 increases to a threshold current ITH, then decreases to zero amps, before immediately beginning to increase once again.
When the current through the inductor L1 exceeds the threshold current ITH, the control IC U1 renders the transistor Q1 non-conductive. The current through the inductor begins to decrease as shown in FIG. 3A. An auxiliary winding L2 is magnetically coupled to the inductor L1 and is provided to a zero-cross detect pin DETIN of the control IC U1 through a resistor R6 (e.g., 22 kΩ). Using the input provided by the zero-cross detect pin DETIN, the control IC U1 is operable to determine when the current through the inductor L1 reaches zero amps. In response, the control IC U1 once again renders the transistor Q1 conductive to begin charging the inductor L1.
It is desirable that a dimming ballast be able to provide a wide range of output power. For example, a single ballast may be required to provide a rather large amount of output power to a lamp (or multiple lamps) at the high-end intensity, and then provide a rather low amount of output power at the low-end intensity (e.g., 1%). If the ballast has a wide range of output power, the ballast must also have a wide range of input power. FIG. 4 is a plot of a desired input power of a dimming ballast versus the intensity of the connected fluorescent lamp. The ballast and the lamp may consume a rather large amount of input power (e.g., 120 W) at the high-end intensity, and a small amount of power (e.g., 6 W) at the low-end intensity (e.g., 1%).
Typical boost converter control ICs (such as the control IC U1) are limited by some specific characteristics, such as a minimum on-time to which the transistor Q1 can be controlled conductive (e.g., 250 nsec). Since the transistor Q1 must be conductive for at least the minimum on-time, the output power of the boost converter cannot drop below a minimum output power level. The input power of the boost converter 26 is equal to the output power of the boost converter plus the losses of the boost converter (e.g., typically 2-3 W). The input power of the ballast 10 is substantially equal to the input power of the boost converter 26. Therefore, the minimum output power level of the boost converter 26 establishes a minimum input power level for the ballast 10, which may be, for example, 10 W if the minimum on-time of the control IC U1 is 250 nsec. For example, if the minimum input power of the control IC U1 is 10 W, the minimum lamp intensity may be approximately 3%, as shown in FIG. 4.
If the lamp 15 is controlled below approximately 3% such that the output power of the boost converter 26 drops below the minimum output power level, the boost converter begins to operate in burst mode, in which additional voltage ripple is generated on the DC bus voltage 32, i.e., across the bus capacitor 30. This voltage ripple can then cause the lamp 15 to flicker. Therefore, the minimum on-time limitation of the control IC U1 affects the range of output power able to be provided by the ballast 10. In other words, if the ballast 10 is designed to drive a high-power lamp, the ballast may not be able dim the intensity of the lamp 15 to a low light level, such as 1% intensity, without flicker.
In order to decrease the input power of the boost converter 26 below the minimum level determined by the minimum on-time limitation of the control IC U1, the boost converter includes the delay circuit 60 to introduce some delay into the operation of the boost converter to thus cause the boost converter to begin operating in discontinuous conduction mode. Referring back to FIG. 2, the phase control input is provided to the delay circuit 60, such that the delay circuit 60 is operable to control the operation of the transistor Q1 in response to the desired intensity of the lamp 15. When the current through the inductor L1 decreases to zero amps, the control IC U1 attempts to render the transistor Q1 conductive by driving the drive pin GTDRV high (i.e., approximately the magnitude of the DC voltage VCC). The delay circuit 60 delays when the transistor Q1 begins to conduct by a delay time tDELAY, which is dependent upon the desired lamp intensity. FIG. 3B is a current waveform 72 of the current through the inductor L1 showing the delay time tDELAY.
The boost converter 26 further comprises a field-effect transistor Q2 having a gate coupled to the drive pin GTDRV of the control IC U1 through a resistor R7 (e.g., 1 kΩ). When the control IC U1 drives the drive pin GTDRV high, the transistor Q2 is rendered conductive and maintains the zero-cross detect pin DETIN at substantially circuit common, such that the control IC U1 continues to maintain the drive pin GTDRV high. Accordingly, the ballast 10 is operable to drive the intensity of the lamp 15 down to approximately 1% since the delay circuit 60 allows the input power of the boost converter 26 to drop below the minimum input power level determined by the minimum on-time of the control IC U1.
FIG. 5 is a simplified schematic diagram of the delay circuit 60. The delay circuit 60 comprises a phase control-to-DC-voltage circuit 62, a gate drive comparison circuit 64, and a drive circuit 66. The delay circuit 60 receives a phase control signal PH_CNTL from the phase control input and a gate drive control signal GATE_DRV from the drive pin GTDRV of the control IC U1. The delay circuit 60 provides a drive signal DLY_OUT to the gate of the transistor Q1.
The phase control signal PH_CNTL is coupled to a negative input of a comparator U10 (e.g., part number LM2903 manufactured by National Semiconductor). A resistor divider comprising two resistors R10, R12 is coupled between the DC voltage VCC and circuit common. For example, the resistors R10, R12 have resistances of 10 kΩ and 2.2 kΩ, such that the resistor divider provides a reference voltage of approximately 2.7 V to a positive input of the comparator U10. When the phase control signal PH_CNTL is below the reference voltage, the output of the comparator U1 is driven to approximately circuit common. When the phase control signal PH_CNTL rises above the reference voltage, the output of the comparator U10 is pulled up to substantially the DC voltage VCC through a resistor R14 (e.g., 10 kΩ). Since the phase control signal PH_CNTL is simply a scaled version of the phase control input provided to the ballast, the output of the comparator U10 is equal to substantially zero volts for a first portion of each half-cycle and equal to substantially the DC voltage VCC for the rest of each half-cycle. In other words, the voltage at the output of the comparator U10 has a duty cycle that is dependent upon the desired intensity of the lamp 15.
The output of the comparator U1 is provided to a low-pass filter, comprising a resistor R16 (e.g., 10 kΩ) and a capacitor C12 (e.g., 10 μF), which filters the output of the comparator to produce a substantially DC voltage. Since the duty cycle of the voltage at the output of the comparator is dependent upon the desired intensity of the lamp 15, the magnitude of the DC voltage produced by the low-pass filter is also dependent upon the desired intensity of the lamp. Therefore, the phase control-to-DC-voltage circuit 62 generates a substantially DC voltage having a magnitude responsive to the phase control signal PH_CNTL.
The filtered DC voltage from the low-pass filter is provided to the gate drive comparison circuit 64, which also receives the gate drive control signal GATE_DRV. The filtered DC voltage is coupled to a negative input of a comparator U12 through a zener diode Z10 having of breakover voltage of, for example, 5.6 V. The negative input of a comparator U12 is coupled to circuit common through a resistor R18 (e.g., 44.2 kΩ). The filtered DC voltage is provided as a reference voltage for the comparator U12.
The gate drive control signal GATE_DRV is coupled to a positive input of the comparator U12 through a resistor R20 (e.g., 6.34 kΩ), which forms a low-pass filter with a capacitor C12 (e.g., 1 nF). When the gate drive control signal GATE_DRV transitions from low to high (i.e., the control IC U1 is attempting to control the transistor Q1 to become conductive), the voltage across the capacitor C12 is initially substantially zero volts and the output of the comparator U12 is held to approximately circuit common. Since the gate drive control signal GATE_DRV is high, the voltage at the positive input of the comparator U12 increases with respect to time. When the voltage at the positive input of the comparator U12 rises above the voltage at the negative input of the comparator (which is dependent upon the desired intensity of the lamp 15), the output of the comparator is allowed to rise up to the gate drive control signal GATE_DRV (i.e., pulled up by a resistor R22, e.g., 10 kΩ). When the gate drive control signal GATE_DRV is once again driven low, the capacitor C12 discharges quickly through a diode D10.
The output of the comparator U12 is provided to the drive circuit 66, which comprises a standard totem-pole structure. The drive circuit 66 comprises an NPN bipolar transistor Q10 (e.g., part number MPSA06) and a PNP bipolar transistor Q12 (e.g., part number 2N3906). The emitters of the transistors Q10, Q12 are coupled together and provide the drive signal DLY_OUT through a resistor R26 (e.g., 100Ω). The junction of the emitters is also coupled to the gate drive control signal GATE_DRV via a diode D12. When the output of the comparator is low, the transistor Q12 pulls the drive signal DLY_OUT down to substantially circuit common. When the output of the comparator U12 is high, the transistor Q10 pulls the drive signal DLY_OUT up to substantially the gate drive control signal GATE_DRV.
Therefore, the low-pass filter comprising the resistor R16 and the capacitor C12 provides an amount of delay into the drive signal DLY_OUT to the transistor Q1. The amount of delay is responsive to the desired intensity of the lamp 15. When the delay circuit 60 introduces the delay into the current through the inductor L1, the boost converter 26 operates in discontinuous conduction mode. Since the boost converter 26 is operating in discontinuous conduction mode, the conduction losses of the boost converter and the THD of the ballast 10 both increase in comparison to when the boost converter is operating in critical conduction mode. However, the ballast 10 is operable to drive the intensity of the lamp 15 down to a low intensity (such as 1%) without flicker from burst mode operation.
FIG. 6 is a plot of the amount of delay provided by the delay circuit 60 versus the desired intensity of the lamp 15. Even though the delay is only required in the current through the inductor L1 when the desired intensity is substantially low, i.e., below 10%, the delay circuit 60 introduces delay into the operation of the boost converter 26 across the dimming range of the lamp 15. Because of limitations of the comparator U10, the filtered DC voltage provided by the phase control-to-DC-voltage circuit 62 cannot be driven to zero volts. Therefore, the drive signal DLY_OUT provided by the delay circuit 60 always have some amount of delay (e.g., 1 μsec). Accordingly, the delay can never be zero seconds and the boost converter 26 can never operate in critical conduction mode.
In order for the ballast 10 to receive a wide range of input voltage (e.g., from approximately 90 to 300 VAC), the resistances of the resistors R10, R12 must be changed in order to change the magnitude of the reference voltage provided to the comparator U10. Therefore, the ballast 10 cannot be offered as a universal-input ballast that is operable to receive a wide range of input voltages.
Thus, there is a need for a universal-input electronic dimming ballast having a boost converter that typically operates in critical conduction mode, but only operates in discontinuous conduction mode when the desired lamp intensity is below a predetermined intensity.